1. Field of the Invention
The present invention relates to a bridge and a data processing method therefor.
2. Description of the Related Art
In an information processing apparatus such as a communication apparatus and an OA equipment, a bus for transferring data at high speed is needed in order to increase the processing speed. As an example of the bus, there is a PCI (Peripheral Component Interconnect) bus. The PCI bus is defined in, e.g., PCI Local Bus Specification and PCI-to-PCI Bridge Architecture Specification. For example, a 33-MHz, 132-MB/s PCI bus with a 32-bit width is used to connect parts within a PC.
Data transactions between a producer 101 and consumer 104 in PCI Local Bus Specification Revision 2.3 will be described using FIG. 1.
Referring to FIG. 1, the producer 101, a flag 102 and a status 103 are connected to PCI bus 1. The consumer 104 and a data unit 105 are connected to PCI bus 0. PCI bus 0 and PCI bus 1 are connected by a PCI-PCI bridge 106.                <Data Transfer from Producer 101 to Consumer 104>        •Operation of Producer 101        P1) When data is generated (or created), the producer 101 writes the data in the data unit 105.        P2) The producer 101 sets the flag 102 indicating completion of the write of the data. Note that this flag 102 will be reset in C2) to be described later.        P3) The producer 101 waits for the status 103 which is written by the consumer 104 upon completion of data processing. In this case, the status 103 is “complete read”.        P4) When the “complete read” status is detected, the producer 101 clears the status 103 (sets the status 103 to “incomplete write”) and starts a next data generation. When the data generation is complete, the operation returns to P1) and repeats P1) to P4).                    •Operation of Consumer 104                        C1) The consumer 104 finds a “set” status of the flag 102 indicating completion of data generation (or creation) of the producer 101.        C2) The consumer 104 resets the flag 102 and processes the data.        C3) When the data processing is complete, the consumer 104 writes the status 103 indicating completion of the data processing. When the write of the status is complete, the operation returns to C1) and repeats C1) to C3).        <Data Transfer from Consumer 104 to Producer 101>        •Operation of Producer 101        P1) The producer 101 prepares a data storage area in the data unit 105.        P2) The producer 101 sets the flag 102 indicating completion of the data storage area preparation. Note that this flag 102 will be reset in C2) to be described later.        P3) The producer 101 waits for the status 103 which is written by the consumer 104 upon completion of data processing. In this case, the status 103 is “complete write”.        P4) When the “complete write” status is detected, the producer 101 clears the status 103 (sets the status 103 to “incomplete read”) and starts a next data storage area preparation. When the data storage area preparation is complete, the operation returns to P1) and repeats P1) to P4).                    •Operation of Consumer 104                        C1) The consumer 104 finds a “set” status of the flag 102 indicating completion of data area preparation of the producer 101.        C2) The consumer 104 resets the flag 102 and processes the data.        C3) When the data processing is complete, the consumer 104 writes the status 103 indicating completion of the data processing. When the write of the status is complete, the operation returns to C1) and repeats C1) to C3).        
FIG. 2 shows an embodiment of the configuration in FIG. 1. In this embodiment, the producer 101 shown in FIG. 1 consists of a primary bus 201, CPU 202 and memory 203. The consumer 104 consists of a secondary bus 204, CPU 205 and memory 207. A DMA accelerator 206 is provided on the secondary bus 204 to perform status transfer by DMA transfer.
The status transfer operation of the system shown in FIG. 2 is as follows. Note that a descriptor indicates a status write address in the primary bus 201, and is embedded with a status write address, a next descriptor address and flag information representing whether or not the next descriptor is valid. Assume that the suitable number of descriptors are prepared in a chain.                (1) A bridge 208 reads a descriptor from the memory 203 on the primary bus 201.        (2) The DMA accelerator 206 reads the descriptor from the bridge 208.        (3) The DMA accelerator 206 also reads a status from the memory 207 on the secondary bus 204.        (4) The DMA accelerator 206 writes the status into the bridge 208.        (5) The bridge 208 writes the status into the memory 203 on the primary bus 201.        (6) The DMA accelerator 206 writes a new descriptor into the bridge 208.        (7) The bridge 208 writes, into the memory 203, a flag indicating completion of the status transfer to the descriptor.        
On the other hand, the techniques for increasing the efficiency of data transfer by a PCI bus and for reducing a processing load on a CPU related to the data transfer by a PCI bus have been proposed (e.g., see Japanese Patent Application Laid-Open No. 9-319698).
However, in the method as the prior art described above in which a DMA accelerator is provided on a secondary bus, and in Japanese Patent Application Laid-Open No. 9-319698, all transactions including status transfer have to be done through a PCI bridge, thereby decreasing the performance.
A DMA accelerator and DMA controller need to operate using a secondary bus, because they are on the secondary bus. Moreover, software management for a PCI bridge and transaction order of DMA is complex.
Also, in the prior art, hardware performance of a secondary bus is low, and a software operation is restricted.
In the prior art, if there is a plurality of functions in a PCI bus, it is impossible to operate them simultaneously. Furthermore, cumbersome processing is needed. For example, a function is executed by making initial settings when a functional operation is started, and negotiation is redone when the operation is switched.
The technique in Japanese Patent Application Laid-Open No. 9-319698 is not suitable for a case in which the amount of data to be transferred is small, e.g., for a case in which a status is transferred.